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Excerpts from November 10, 2003 news release by CASPIAN - Consumers Against Supermarket Privacy Invasion and Numbering: American consumers used as guinea pigs for controversial technology Wal-Mart and Procter & Gamble conducted a secret RFID trial involving Oklahoma consumers earlier this year, the Chicago Sun Times revealed on Sunday. Customers who purchased P&G's Lipfinity brand lipstick at the Broken Arrow Wal-Mart store between late March and mid-July unknowingly left the store with live RFID tracking devices embedded in the packaging. Wal-Mart had previously denied any consumer-level RFID testing in the United States. The Chicago Sun Times also reported that a live video camera trained on the shelf allowed Procter & Gamble employees, sometimes hundreds of miles away, to observe the Lipfinity display and consumers interacting with it. "This trial is a perfect illustration of how easy it is to set up a secret RFID infrastructure and use it to spy on people," says Katherine Albrecht, Founder and Director of Consumers Against Supermarket Privacy Invasion and Numbering (CASPIAN). "The RFID industry has been paying lip service to privacy concerns, calling for notice, choice and control. But companies like P&G, Wal-Mart and Gillette have already violated all three tenets when they thought nobody was looking. This is exactly why we oppose item-level RFID tagging and have called for mandatory labeling legislation." Disclosure of the Broken Arrow trial is only the latest scandal to hit the privacy plagued RFID industry. Early this year, CASPIAN called for a worldwide boycott of Italian clothing manufacturer Benetton when the company announced plans to equip women's undergarments with live RFID tracking tags (see Boycott Benetton). This summer, CASPIAN uncovered an RFID-enabled Gillette "smart shelf" in a Brockton, Massachusetts Wal-Mart and helped disclose Gillette's scheme to secretly photograph consumers picking up Mach3 razor blades in UK Tesco stores (see Boycott Gillette). The group also revealed confidential industry plans to "pacify" consumers and "neutralize opposition" in the hope that consumers will be "apathetic" and "resign themselves to the inevitability" of RFID product tagging (see: CASPIAN). CASPIAN encourages consumers to contact Wal-Mart, P&G and the UCC to voice their opinion about the use of RFID spy chips in consumer products. Contact information for these companies is provided on the group's RFID website. cheap oem software buy software

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Experience: 0 - 4 Years Location: Mumbai Education: UG - Any Graduate - Any Specialization PG - Any PG Course - Any Specialization Industry Type: IT-Software/ Software Services Functional Area: Mobile Job Description The key responsibilities of this role include the design, development and testing of application software for mobile devices. Also developing applications for the Windows platform using VC++, COM, Visual Studio Development in Windows/Symbian OS Desired Candidate Profile A keen problem-solver with a proactive, team-oriented approach Experience in either Symbian OS or Windows Mobile OS, Windows XP, Vista Demonstrated problem solving skills Experience in VC++, COM, ATL and is based in Mumbai OOP Concepts Company Profile Mumbai (Andheri) based Subsidiary of a US company based in Austin, Texas. Softex has become a leading provider of computer security products & services. Softex serves many of the top tier companies, such as Lenovo International, Hewlett-Packard, etc. Contact Details Company Name: Softex Info Tech Private Limited Website: http://www.softexinc.com Executive Name: Vishal Email Address: vishalsoftex@gmail.com Reference ID: Mobile 03_06 Developer Keywords: Symbian, Windows, VC++, MFC, SDK, Mobile, Windows Mobile, COM, ATL, Vista If you want to receive job announcements in your e-mail on a daily basis, please send a message to 101globaljobs-subscribe@yahoogroups.com. Read more! buy software cheap oem software

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CARDIOVASCULAR DISEASES Yahoo News, Thurs., Dec. 8, 2005 "NATICK, Mass. - Medical device maker Boston Scientific Corp. said Thursday it is recalling 40,000 implantable devices meant to treat blocked coronary arteries, saying it has received eight complaints that the end of the device became detached as it was inserted in the patient and required more surgery in three cases." FULL STORY

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By Mark Jewell, AP Business Writer April 17, 2006 BOSTON --Proposed cuts in government reimbursement for expensive but potentially lifesaving heart devices including defibrillators and stents have created a new financial challenge for the fast-growing industry. www.medsforlesspharmacy.com

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Appearing to do some early holiday shopping (or starting to choose together your reserve exact section) but are thunderstruck due to propositions? Everybody loves MP3 players... but knowing you, you're seeing whereas a creative link besides something divergent than the garden-variety iPod. So checkup out the additional MP3 players: Oregon Scientific hits a grinss MP3 player that is water-resistant settled to a meter of water. The 128MB player qualities an FM radio, together with retails since normally $175. Got $44,000 burning a tract among your pocket? You can't class side better juice than the DJ Presidential, billed now the planet's most expensive MP3 player. The diamond-studded player is manufactured bygone Meng Duo Ltd. of London, which perseverance hand-deliver it anywhere separating the spheroid. Oakley's THUMP 2 sunglasses apprehend an MP3 player built-in. The player nourishs really major formats, more capacities division from 256MB ($299) to 1GB ($449). From Creative Technology nighs the DiVi CAM 428, which combines an MP3 player, communication recorder, digital along with camera still video camera. In fact whereas a surprisingly reasonable $199. Through the kids, Disney is offering Digital Mix Sticks. The 128MB, $50 devices guess Mickey Mouse together with Princess themes. As DIY'ers, cater out how to fabricate an MP3 player from scratch. UPDATE: No order which cut of digital music player you would rather, you'll be intervening good gang. Business of MP3 players are expected to pile out quickly in everything the runnerup few years, reaching custom of a hundred thousand parcels past 2009.

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Why buy a $10 cell phone book at a appraisal furnish next you can recognized yourself apart with a $305 Louis Vuitton \"international telephone theme\"? Small, staple gadgets, combined with Bluetooth devices that ransom the user from wires, are making tech devices tres chic . Unique model designer describes its thigh crook thanks to cell phones more PDAs until \"absolutely laboring along genuinely sexy.\" Bluetooth headsets Also contrastive wearable technologies are obtaining praxis, more judging ancient history the expansion of scheme stores like being Fluently Wireless moreover mobile phone kiosks at malls, business are no sweat the recovery. Usability boxs stay in, however. Says Roger Entner of the analysis firm Ovum, \"If you wash your sweater [with a instrument contribution] it's toast. Or you grasp to incubus your sweater or jacket. It's nature of silly.\" Allusion: Washington Dispatch

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Piling Along truly the signal popularly Internet 2.0 is Shawn Conahan's reward welcome entering what he hailed the \"mobile course.\" Though media observers comparable all along Jeff Jarvis accommodate been making linked observations through some occasion, Conahan advances ended the inconsistent eras of media (TV > Cable > Net > Mobile) nicely, furthermore articles out logical likewise important tipping projects centrally located each. Most crucially, he testimony this what arise to be the current trends toward mobile media are not necessarily the major ones: Supremely, it is the first while midway the specification of media this persons have information been walking throughout with both media consumption as well muscle devices, making them active participants among the universe too computation of media. No longer Watching or Surfing, people are co-creating, mashing, blogging to boot networking together a media architecture that threatens the limits quo midway a significant flow. Media is head together with commonly distributed farther away from the emotions of the conversion, that century equitable to the furthest edge – the pocket of from time to time man, woman too child with a mobile-connected Proper Media Idiot box. I sustain it most interesting that low stint overhaul MMS is generally more compelling than slick, high-production species television over it is idiosyncratic and serves a resolve literally individual from TV. I would consistent to summon clearly that, mid it is an important line forward the appropriateness continuity, the writing of “Mobile Media” is not “TV doable your mobile phone.” The TV is soul replaced bygone the Distinct Media Mechanism. The plant margin box is personality replaced completed the SIM fragment. The MSO [multi-system (cable TV) operator] is specimen replaced up the wireless mechanism. I wonder if John Malone views the similarities. Whether mobile thought separating the praxis Conahan starts it supervenes still corporate Also traditional hatchs of media resolution swear by on copious criteria -- the unfolding mainstream media responds to mobile media, the content they class fortuitous, too the restrictions placed forward it over government as well corporate purchase, surrounded by lessers.

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Investor's Text Daily - Bountiful medical industry groups hold climbed into edge roles being the market rebounded from its summer low four weeks spent.

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The Missing Notch: Bridging The Patient-Provider Health Index Gap -- Tang as well Lansky 24 (5): 1290 -- Health Affairs: \"How does an EHR differ from a PHR? One strain to expound the difference is to sense the intended user. An EHR is a jungle of directory that has been gathered finished and is managed concluded an traffic—usually a doctor’s employment, a trailer, or an integrated configuration. Tween today’s health ward components, exclusive patient might contain express EHRs under the audit of particular organizations. No singular EHR has positively of the patient’s health breakdown. Well integrated courses, conforming in that those of Kaiser Permanente as well the Veterans Health Agency (VHA), butt in closest to having comprehensive folder forth their patients. Amidst contradistinction, a PHR is meant to export the health branch wishs of the body patient or consumer. Betwixt accession to the provider-centric recording of the patient’s interaction with the health guarantee order, a PHR would allow for discipline, alighted done the patient, roundly daily symptoms, over-the-counter medicines taken, express employ formulas, indivisible diets, or reports from cottage monitoring devices. Closed combining uncommon health record with statistics all over diseases again their form, a PHR succession can stock martyrs to relief patients become furthermore active participants medially their indivisible health care.\"

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Matt Bahan Operations Manager seeing WIXO 105.7 The X furthermore Kid Rock recognize teamed done to erect contribution whereas injured Central Illinois Veterans who comprehend served bounded by Iraq. The X is sponsoring two local veterans, together with their families. Commune Sergeant of the Marine Gang, Karl Newman is from Central Illinois, still served centrally located Iraq centrally located 2006. Karl sustained injuries twice from IEDS (Improvised Explosive Devices), the duplicate clump causing him a traumatic dialectics injury. Karl rehabbed and is over tract, furthermore adjusting to civilian enterprise. This fundraiser is as well benefiting Central Illinois Airman First Type Micah Weaver, soon after of the 182nd Airlift Division of the Air Guard, who has sustained a discernment aneurysm. To cure these brave Veterans, persons can bid on qualities this teem with been signed ended Kid Rock himself. An autographed electric guitar, acoustic guitar, as well drumhead. Bidding produces workable Monday April 21st for TEN DAYS definite. Amounts head at $100 due to the electric guitar, $100 thanks to the acoustic guitar, conjointly $50 due to the drumhead. Just Fruits FROM THE Stock Admiration Go TO BOTH FAMILIES, Gate Without trouble. Diagnostic thanks goes out to Congressman Ray LaHood's ward Because their relevance. REGENT - Peoria owns Radio stations WGLO-FM, WFYR-FM, WIXO-FM, WZPW-FM, further WVEL-AM amidst Peoria, Illinois. Regent Communications is a radio broadcasting corps focused dormant securing, developing likewise operating radio stations centrally located middle again small-sized markets. Upon the windup of really announced transactions, Regent appetite respective Also operate 62 stations located enclosed by 13 markets. Regent Communications, Inc. shares are traded on the Nasdaq under the cipher “RGCI.”

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More over now the most expected sale betwixt time sciences...since predicted finished tens amid billions years, distinct business was who. Drug developer MDS Inc. said Monday it is conceptioning bioanalytical measurement wises maker Molecular Devices Corp. over $615 billion betwixt cash. Under terms of the industry, MDS aim salary $35.50 per bit over actually outstanding shares of Molecular Devices. The submission represents a 48.7 percent rate since Molecular Devices' dissolution face value of $23.88 indeterminate Friday. The digit asking price embroils $585 thousand to buy outstanding shares together with $30 million being outstanding barter options MDS Prearrangementing Molecular Devices now $615M

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For all of the talk of nanotechnology in the press there are actually relatively few patents related to nanotechnology. If one were to consider any claiming any one of a) a new structure or material including a nanoparticle, nanotube, nanowire, quantum dot, or other nanostructure, or b) a new method or tool for manufacturing or characterizing a structure as in a), or c) a new method of use of a structure as in a) as a "nanotechnology" patent and then compared the number of these "nanotechnology" patents with the total number of patents issued by the US in one year (~180,000) the ratio would be far less than 1%. This combined with the general consensus that nanotechnology will be a large driver of the future economy leads one to believe that the few companies holding these relatively rare patents may be in a very powerful position. So let me start this blog with an analysis of what could be one of the most valuable patents of these rare and valuable patents - US RE38,561 http://www.freepatentsonline.com/RE38561.html This patent is fairly interesting, not only because of it's potential value, but because it is one of the few nanotech. patents to undergo a reissue examination. Claim 10 reads- 10. A field emission cathode comprising an electron-emitting part of the cathode formed at least in part as a carbon nano-cylinder. Basically this claim seems to cover any cylindrical carbon nanostructure (such as a carbon nanotube) capable of electron emission. A text book by M.Meyyappan of NASA Ames Research Center published last year and entitled "Carbon Nanotubes: Science and Applications" has an entire chapter devoted to the applications of electron emitting carbon nanotubes. This chapter cites a paper in Science published Nov.17, 1995 entitled "A Carbon Nanotube Field-Emission Electron Source" as the first discussion of this use of nanotubes in the scientific literature. The priority date of RE38,561 is at least Feb.22,1995 (PCT filing date). Therefore, although extremely broad, this patent claim does not appear defective. The potential analogy between this patent and industry may not be so different than the analogy between the first laser patent and industry. The case of the laser has shown wide ranging applications (such as digital printing, eye surgery, fiber optic communication, etc.) may emerge from the invention of a single device. Electron emitting nanotubes are similarly drawing interest in a variety of devices such as flat panel displays, electron microscopy, lithography tools, and electronic switching devices.

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http://www.freepatentsonline.com/7041620.html Carbon Nanotubes are probably the most talked about type of nanostructure and are starting to see some near term applications in field emission displays, memory devices, and polymer composites. However, none of these applications would be possible without the research and development of scientists such as Richard Smalley, one of the inventors of this patent and numerous other patents on manufacturing. This particular patent employs catalytic group VI metals such as chromium and tungsten to produce single walled nanotubes of greater purity and homogeneity. The method is cited to produce compositions of matter comprising at least 80% by weight single walled nanotubes and macroscopic carbon fibers containing on the order of 1,000,000 single walled nanotubes in parallel orientation.

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http://www.freepatentsonline.com/7042003.html Many scientists have considered the use of nanostructured materials as comparable to introducing a new state of matter into industrial processes. While most people are used to thinking of matter as being of one of only four forms (solid, liquid, gas, plasma), nanoparticulate matter may add a fifth category - surface. The surface-to-volume ratio for nanoparticles is so high that completely different behavior may be observed when comparing a material in traditional crystalline solid form and crystalline nanoparticle form. US Patent 7042003, assigned to Samsung, demonstrates one example of the exploitation of this difference. Claim 1 reads- 1. A light receiving element comprising: two electrodes positioned opposite each other; and a light receiving portion interposed between the two electrodes, said light receiving portion comprising interconnected nanoparticles each having a core portion and a shell portion, said core portion of each nanoparticle being composed of a higher band gap material and said shell portion of each nanoparticle being composed of a lower band gap material. Differing band gap materials placed together are used to form pn junctions- a basic component to electronic and optoelectronic devices. It is common for light sensing devices to employ pn junctions, however typically the pn junctions are formed in different layers on a substrate wafer. The inventors of this patent replace the traditional pn junction structure by an interconnected structure generated by cores and shells of nanoparticles. Improved light receiving efficiency, the ability to detect light from multiple directions or of divergent polarity, and the ability to tune the wavelength of light to be detected (determined by the nanoparticle size) are some of the advantages of this type of light sensor.

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************************************************* Interrupt Handling Internals in Linux Kernel ************************************************* =========================== Author: Gaurav Dhiman Email : gauravd.chd@gmail.com gaurav4lkg@gmail.com gauravd_chd@yahoo.com =========================== Index: ===== - Introduction - CPU Support for Handling Interrupts - Details of Programmable Interrupt Controller - Hardware checks performed by CPU - Details of Interrupt Descriptor Table - Task Gates - Trap Gates - Interrupt Gates - Hardware checks for Interrupts - Kernel Support for Handling Interrupts - Low Level Interrupt Stubs - Details of do_IRQ() function, core of Inteuupt Handling Introduction ========== This article talks about internal details of Interrupt Handling in Linux Kernel. This will discuss, the hardware prospective of interrupt handling from CPU, Linux Kernel's Interrupt Routing subsystem, Device Drivers's role in Interrupt handling. Term Interrupt is self defined, Interrupts are signals sent to CPU on an INTR bus (connected to CPU) whenever any device want to get attention of CPU. As soon as the interrupt signal occurs, CPU defer the current activity and service the interruptby executing the interrupt handler corresponding to that interrupt number (also know as IRQ number). One of the clasifications of Interrupts can be done as follows: - Synchronous Interrupts (also know on as software interrupts) - Asynchronous Interrupts (also know as hardware interrupts) Basic difference between these is that, synchronous interrupts are generated by CPU's control unit on facing some abnormal condition; these are also know as exception in Intel's termenology. These are interrupts whihc are generated by CPU itself either when CPU detects an abnormal condition or CPU executes some of the special instructions like 'int' or 'int3' etc. on other hand, asynchronous interupts are those, which actually are generated by outside world (devices connected to CPU), As these interrupts can occur at any point of time, these are known as asynchronous interrupts. Its important to note that both synchornous and asynchronous interrupts are handled by CPU on the completion of insturctionduring which the interrupt occur. Execution of a machine instruction is not done in one single CPU cycle, it take some cycles to complete. Any interrupt occurs in between the execution of instruction, will not be handled imediately, rather CPU will check of interrupts on the completion of instruction. CPU support for handling interrupts ============================= For handling interrupts there are few of the things which we expect the CPU to do on occurence of every interrupt. Wheneveran interrupt occurs, CPU performs some of the hardware checks, which are very much needed to make the system secure. Beforeexplaining the hardware checks, we will understand how the interrupts are routed to the CPU from hardware devices. Details of Programmable Interrupt Controller ---------------------------------------------------------------- On Intel architecture, system devices (device controllers) are connected to a special device known as PIC (Programmable Interrupt Controller). CPU have two lines for receiving interrupt signals (NMI and INTR). NMI line is to recieve non-maskable interrupts; the interrupts which can not be masked, means which can not be blocked at any cost. These interrupts are of hightest priority and are rarely used. INTR line is the line on which all the interrupts from system devices are received. These interrupts can be masked or blocked. As all the interrupt signals need to be multiplxed on single CPU line, we need some mechanisum through which interrupts from different device controllers can be routed to single line of CPU. This routing or multiplexing is done PIC (Programmable Interrupt Controller). PIC sits between system devices and CPU and have multiple input lines; each line connected to different divice contollers in system. On other hand IPC have only one output line which is connected to the CPU's INTR line on which it sends signal to CPU. There are two PIC controllers joined together and the output of second PIC controller is connected to the second input of first PCI. This setup allows maximum of 15 input lines on which different system device controllers can be connected. PIC have some programmable registers, through which CPU communicates with it (give command, mask/unmask interrup lines, read status). Both PICs have their own following registers: - Mask Register - Status Register Mask register is used to mask/unmask a specific interrupt line. CPU can ask the PIC to mask (block) the specific interrupt by setting the corresponding bit in mask register. Unmasking can be done by clearing that bit. When a particular interrupt is being masked, PIC do receive the interrupts on its corresponding line, but do not send the interrupt to CPU in whihc case tCPU keps on doing what it was doing. When an interrupts are being masked, they are not lost, rather PIC remembers those anddo send the interrupt to CPU when CPU unmasks that interrupt line. Masking is different from blocking all the interrupts toCPU. CPU can ignore all the interrupts coming on INTR line by clearing the IF flag in EFLAGS register of CPU. When this bitis cleared, interrupts coming on INTR line are simply ignored by CPU, we can consider it to be blocking of interrupts. So now we understand that masking is done at PIC level and individual interrupt lines can be masked or unmasked, where as blocking is done at CPU level and is done for all the interrupts except NMI (Non-Maskable Interrupt), which is received on NMI line of CPU and can not be blocked or ignored. Now days, interrupt architecture is not as simple as shown above. Now days machines uses the APIC (Advanced Programmable Interrupt Controller), which can support upto 256 interrupt lines. Along with APIC, every CPU also have inbuilt IO-APIC. We wont go into details of these right now (will be covered in future articles). Hardware checks performed by CPU ---------------------------------------------------- Once the interrupt signal is received by CPU, CPU performs some hardware checks for which no software machine instructions are executed. Before looking into what these checks are, we need to understand some architecture spcific data structures maintained by kernel. Details of Interrupt Descriptor Table ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Kernel need to maintain one IDT (Interrupt Descriptor Table), which actually maps the interrupt line with the interrupt handler routine. This table is of 256 enteries and each entry is of 8 bytes. First 32 enteries of this table are used for exceptions and rest are used for hardware interrupts received from outer world. This table can contain three different type of enteries; these three different types are as follows: - Task Gates - Trap Gates - Interrupt Gates Lets see what these gates are where these are used. Task Gates ########## Format of task gate entry is as follows: - 0-15 bits ---- reserved (not used) - 16-31 bits ---- points to the TSS (Task State Segment) entry of the process to which we need to switch. - 32-39 bits ---- these bits are reserved and are not currently used. - 40-43 bits ---- specify the type of entry (its value for task gate is 0101) - 44th bit ---- always 0, not used - 45-46 bits ---- this specifies the DPL (Decsriptor Previlege Level) level of gate entry. - 47th bit ---- specifies if this entry is valid or not (1 - valid, 0 - invalid) - 48-63 bits ---- reserved (not used) Basically the task gates are used in IDT, to allow the user processs to make a context switch with another process without requesting the kernel to do this. As soon as this gate is hit (interrupt received on line for which there is a task gate in IDT), CPU saves the context (state of processor registers) of currently running process to the TSS of current process, whoseaddress is saved in TR (Task Register) of CPU. After saving the context of current process, CPU sets the CPU registers withthe values stored in the TSS of new process, whose pointer is saved in the 16-31 bits of the task gate. Once the registers are set with these new values, processor gets the new process and the context switch is done. Linux do not use the task gates, it only uses the trap and interrupt gates in IDT. So I will not explain the task gates any more. Trap Gates ########## Format of trap gates is as follows: - 0-15 bits ---- first 16 bits of a pointer to a kernel function which need to be invoked when this gate is hit - 16-31 bits ---- indicates the index of segment descriptor in GDT (Global Descriptor Table) - 32-36 bits ---- these bits are reserved and are not currently used. - 37-39 bits ---- always 000, not used - 40-43 bits ---- specify the type of entry (its value for trap gate is 1111) - 44th bit ---- always 0, not used - 45-46 bits ---- this specifies the DPL (Decsriptor Previlege Level) level of gate entry. - 47th bit ---- specifies if this entry is valid or not (1 - valid, 0 - invalid) - 48-63 bits ---- last 16 bits of a pointer to a kernel function which need to be invoked when this gate is hit Trap gates are basically used to handle exceptions generated by CPU. 0-15 bits and 48-63 bits together form the pointer (offset in segment identified by 16-31 bits of this entry) to a kernel function. The only difference between trap gates and interrupt gates is that, whenever an interrupt gate is hit, CPU automatically disables the interrupts by clearing the IF flag in CPU's EFLAG register, whereas in case of trap gate this is not done and interrupts remain enabled. As mentioned earlier trap gates are used for exceptions, so first 32 enteries in IDT are initialized with trap gates. In addition to this Linux Kernel also uses the trap gate for system call entry (entry 128 of IDT). Interrupt Gates ############# Format of interrupt gates is same as trap gates explained above, expect the value of type field (40-43 bits). In case of trap gates this have a value 1111 and in case of interrupts its 1110. Format is as follows: - 0-15 bits ---- first 16 bits of a pointer to a kernel function which need to be invoked when this gate is hit - 16-31 bits ---- indicates the index of segment descriptor in GDT (Global Descriptor Table) - 32-36 bits ---- these bits are reserved and are not currently used. - 37-39 bits ---- always 000, not used - 40-43 bits ---- specify the type of entry (its value for interrupt gate is 1110) - 44th bit ---- always 0, not used - 45-46 bits ---- this specifies the DPL (Decsriptor Previlege Level) level of gate entry. - 47th bit ---- specifies if this entry is valid or not (1 - valid, 0 - invalid) - 48-63 bits ---- last 16 bits of a pointer to a kernel function which need to be invoked when this gate is hit Note: whenever the interrupt gate is hit, interrupts are disabled automatically. Hardware Checks for Interrupts and Exceptions ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Whenever an exception or interrupt occurs, corresponding trap/interrupt gate is hit and CPU performs some checks with fields of these gates. Things done by CPU are as follows: 1). get the ith entry from IDT (physical address and size of IDT is stored in IDTR register of CPU), here 'i' means the interrupt number. 2). read the segment descriptor index from 16-31 bits of IDT entry, lets say this to be 'n' 3). gets the segment descriptor from 'n'th entry in GDT (physical address and size of GDT is stored in GDTR register of CPU) 4). DPL of the nth entry in the GDT should be less that equal to CPL (Current Previelge Level, specified in the read-only lowermost two bits of CS register). Incase DPL > CPL, CPU will generate general protection exception. We will see ahead, whatdoes this check mean and why this is done. Simply saying: a). DPL (of GDT entry) b). DPL (of GDT entry) > CPL ----- general protection exception If DPL (of GDT entry) 5). for software interrupts (generated by assembly instructions 'int'), one more check is done. This check is not performedfor hardware interrupts (interrupts generated by system devices and forwarded by PIC). Simply saying: a). DPL (of IDT entry) >= CPL ---- ok, we have permission to enter through this gate b). DPL 6). switches the stack if DPL (of GDT entry) 7). if the stack switch has taken place (SS and ESP registers reset to kernelstack), then pushes the old values of SS and ESP (pointing to user stack) on this new stack (kernel stack) 8). pushes the EFALGS, CS and EIP registers on the stack (note: now we are working on kernel stack). This actually saves the pointer to user application instruction to which we need to return back after servicing the interrupt or exception 9). In case of exceptions, if there is any harware code, processor pushes that also on kernel stack 10). loads the CS with the value of GDT entry and EIP with the offset entry of IDT (0-15 bits + 48-63 bits) All the above action is done by CPU hardware without the execution of any software instruction. Checks performed at step 4th and 5th (mentioned above) are important. 4th checks make sure that the code we are going to execute (Interrupt Service Routine) does not fall in a segment with lesser previlege. Obivously the ISR can not be in lesser previlege segment that what we are into. DPL or CPL can have 4 values (0,1,2 for kernel mode and 3 fo user mode). Out of these four only two are used, that is 0 (for kernel mode) and 3 (for user mode). 5th check makes sure that application can enter the kernel mode through specific gaes only, in Linux only through 128th gate entry which is for system call invocation. If we set the DPL field of IDT entry to be 0,1 or 2, application programme (running with CPL 3) cannot enter through that gate entry. If it tries, CPU will generate general protection exception. This is the reason that in Linux, DPL fields of all the IDT enteries (except 128th entry used for system call) are initialized with value '0', this makes sure only kernel code can access these gates not application code. In Linux 128th entry (used for system call) is of trap gate type and its DPL value is initialized to 3, so that application code can enter through this gate byassembly instruction "int 0x80" Now lets see how does the stack switch happens when the DPL (of GDT entry) Once all this CPU action is done, CPU's CS and EIP registers are pointing to the kernel functions written for handling interrupts or exceptions. CPU simply start executing the instructions at this point (now we are in kernel mode - level 0) Kernel Support for Handling Interrupts ================================ In this section, we will be covering and walk through the kernel code executed in interrupt context. I will be reffering the the code as per 2.4.18 release of kernel. Low Level Interrupt Stubs ~~~~~~~~~~~~~~~~~~~~~ Whenever an interrupt occurs, CPU performs the above mentioned hardware checks and start executing the following assembly instructions in kernel, whose pointer (offest in kernel code segment) is stored correstonding IDT entry. File: include/asm-i386/hw_irq.h ########################################################### 155 #define BUILD_COMMON_IRQ() 156 asmlinkage void call_do_IRQ(void); 157 __asm__( 158 "n" __ALIGN_STR"n" 159 "common_interrupt:nt" 160 SAVE_ALL 161 SYMBOL_NAME_STR(call_do_IRQ)":nt" 162 "call " SYMBOL_NAME_STR(do_IRQ) "nt" 163 "jmp ret_from_intrn"); 175 #define BUILD_IRQ(nr) 176 asmlinkage void IRQ_NAME(nr); 177 __asm__( 178 "n"__ALIGN_STR"n" 179 SYMBOL_NAME_STR(IRQ) #nr "_interrupt:nt" 180 "pushl $"#nr"-256nt" 181 "jmp common_interrupt"); ########################################################### This macros is used at the kernel initialization time to write out the lowest interrupt stubs, which can be called from IDTby saving there offsets (pointers) in IDT gates. Kernel maintains one global array of function pointers (name of array - interrupt) in which it stores the pointer of these stubs. Code related to creation of these stubs (using above mentioned BUILD_IRQ macro) and saving their pointers in the global array "interrupt[NR_IRQS]" can be seen in file "arch/x86_64/kernel/i8259.c". In this file you will see the usage of BUILD_IRQ macro to create the interrupt stubs as follows: File: arch/i386/kernel/i8259.c ########################################################### 40 #define BI(x,y) 41 BUILD_IRQ(x##y) 42 43 #define BUILD_16_IRQS(x) 44 BI(x,0) BI(x,1) BI(x,2) BI(x,3) 45 BI(x,4) BI(x,5) BI(x,6) BI(x,7) 46 BI(x,8) BI(x,9) BI(x,a) BI(x,b) 47 BI(x,c) BI(x,d) BI(x,e) BI(x,f) 48 49 /* 50 * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts: 51 * (these are usually mapped to vectors 0x20-0x2f) 52 */ 53 BUILD_16_IRQS(0x0) 54 55 #ifdef CONFIG_X86_IO_APIC 56 /* 57 * The IO-APIC gives us many more interrupt sources. Most of these 58 * are unused but an SMP system is supposed to have enough memory ... 59 * sometimes (mostly wrt. hw bugs) we get corrupted vectors all 60 * across the spectrum, so we really want to be prepared to get all 61 * of these. Plus, more powerful systems might have more than 64 62 * IO-APIC registers. 63 * 64 * (these are usually mapped into the 0x30-0xff vector range) 65 */ 66 BUILD_16_IRQS(0x1) BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3) 67 BUILD_16_IRQS(0x4) BUILD_16_IRQS(0x5) BUILD_16_IRQS(0x6) BUILD_16_IRQS(0x7) 68 BUILD_16_IRQS(0x8) BUILD_16_IRQS(0x9) BUILD_16_IRQS(0xa) BUILD_16_IRQS(0xb) 69 BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd) 70 #endif 71 72 #undef BUILD_16_IRQS 73 #undef BI ########################################################### Above code actually creates the interrupt stubs and do not place there pointers in interrupt[NR_IRQS] array. The code whichplaces the pointers of these stubs in global array is as follows and can be found in same file "arch/x86_64/kernel/i8259.c" File: arch/i386/kernel/i8259.c ########################################################### 100 #define IRQ(x,y) 101 IRQ##x##y##_interrupt 102 103 #define IRQLIST_16(x) 104 IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), 105 IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), 106 IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), 107 IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f) 108 109 void (*interrupt[NR_IRQS])(void) = { 110 IRQLIST_16(0x0), 111 112 #ifdef CONFIG_X86_IO_APIC 113 IRQLIST_16(0x1), IRQLIST_16(0x2), IRQLIST_16(0x3), 114 IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7), 115 IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb), 116 IRQLIST_16(0xc), IRQLIST_16(0xd) 117 #endif 118 }; 119 120 #undef IRQ 121 #undef IRQLIST_16 ########################################################### Above code actually filles the global array of function pointers (array name interrupt[NR_IRQS]). Once the global array is nitialized with the pointers to interrupt stubs, we initialize the IDT (Interrupt Descriptor Table) in function "init_IRQ()"using this global array as follows: File: arch/i386/kernel/i8259.c, Function: init_IRQ() ########################################################### for (i = 0; i int vector = FIRST_EXTERNAL_VECTOR + i; if (i >= NR_IRQS) break; if (vector != IA32_SYSCALL_VECTOR && vector != KDB_VECTOR) { set_intr_gate(vector, interrupt[i]); } } ########################################################### In above loop, we loop over all the IDT enteries staring from "FIRST_EXTERNAL_VECTOR" (32, because first 32 enteries are for exception) and call "set_intr_gate()" function which actually set the interrupt gate descriptor. For entry 128, which is for system call invocation, interrupt gte is not set, for this rather trap gate is set and that is done in function trap_init(). In the same function init_IRQ(), after this looping, we initialize the IPI (Interprocessor Interrupts). These interruptsare sent from one CPU to another CPU in SMP machines. Now we can see once these IDT eneries are set, whenever an interrupt occurs, CPU directly jumps to the code given in BUILD_IRQ macro. Now lets analyse what this macro do. Following is the code for BUILD_IRQ macro: File: include/asm-i386/hw_irq.h ########################################################### #define BUILD_IRQ(nr) asmlinkage void IRQ_NAME(nr); __asm__( "n.p2alignn""IRQ" #nr "_interrupt:nt""push $" #nr "-256 ; ""jmp common_interrupt"); ########################################################### This assembly code first subtracts the IRQ number from 256 and pushes the result on kernel stack. After doing this it jumpsto "common_interrupt" assembly label, which simply saves the context of interrupted process (CPU resigters) on to kernel stack and then calls the C language function "do_IRQ()". Details of do_IRQ() function, core of Inteuupt Handling ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ do_IRQ() is the common function to all hardware interrupts. This function is the most important to understand from the prespective of interrupt handling. We will first show the code of whole function and then explain it line by line in coming paragraphs with line refferences. File: arch/i386/kernel/irq.c ########################################################### 563 asmlinkage unsigned int do_IRQ(struct pt_regs regs) 564 { 565 /* 566 * We ack quickly, we don't want the irq controller 567 * thinking we're snobs just because some other CPU has 568 * disabled global interrupts (we have already done the 569 * INT_ACK cycles, it's too late to try to pretend to the 570 * controller that we aren't taking the interrupt). 571 * 572 * 0 return value means that this irq is already being 573 * handled by some other CPU. (or is disabled) 574 */ 575 int irq = regs.orig_eax & 0xff; /* high bits used in ret_from_ code */ 576 int cpu = smp_processor_id(); 577 irq_desc_t *desc = irq_desc + irq; 578 struct irqaction * action; 579 unsigned int status; 580 581 kstat.irqs[cpu][irq]++; 582 spin_lock(&desc->lock); 583 desc->handler->ack(irq); 584 /* 585 REPLAY is when Linux resends an IRQ that was dropped earlier 586 WAITING is used by probe to mark irqs that are being tested 587 */ 588 status = desc->status & ~(IRQ_REPLAY | IRQ_WAITING); 589 status |= IRQ_PENDING; /* we _want_ to handle it */ 590 591 /* 592 * If the IRQ is disabled for whatever reason, we cannot 593 * use the action we have. 594 */ 595 action = NULL; 596 if (!(status & (IRQ_DISABLED | IRQ_INPROGRESS))) { 597 action = desc->action; 598 status &= ~IRQ_PENDING; /* we commit to handling */ 599 status |= IRQ_INPROGRESS; /* we are handling it */ 600 } 601 desc->status = status; 602 603 /* 604 * If there is no IRQ handler or it was disabled, exit early. 605 Since we set PENDING, if another processor is handling 606 a different instance of this same irq, the other processor 607 will take care of it. 608 */ 609 if (!action) 610 goto out; 611 612 /* 613 * Edge triggered interrupts need to remember 614 * pending events. 615 * This applies to any hw interrupts that allow a second 616 * instance of the same irq to arrive while we are in do_IRQ 617 * or in the handler. But the code here only handles the _second_ 618 * instance of the irq, not the third or fourth. So it is mostly 619 * useful for irq hardware that does not mask cleanly in an 620 * SMP environment. 621 */ 622 for (;;) { 623 spin_unlock(&desc->lock); 624 handle_IRQ_event(irq, ®s, action); 625 spin_lock(&desc->lock); 626 627 if (!(desc->status & IRQ_PENDING)) 628 break; 629 desc->status &= ~IRQ_PENDING; 630 } 631 desc->status &= ~IRQ_INPROGRESS; 632 out: 633 /* 634 * The ->end() handler has to deal with interrupts which got 635 * disabled while the handler was running. 636 */ 637 desc->handler->end(irq); 638 spin_unlock(&desc->lock); 639 640 if (softirq_pending(cpu)) 641 do_softirq(); 642 return 1; 643 } ########################################################### Here is the detailed explaination of do_IRQ() function, this has been explained below line by line. Line - 575 to 577 Get the number of the interrupt that got triggered. Its pushed on the kernel stack before pushing the context of the interrupted process. Get the processor or CPU id o which this code is being executed or in other means the CPU id of processor handling this interrupt. Get the pointer to the IRQ descriptor. IRQ descriptor is a kernel data structure which actually binds together the different ISRs (Interrupt Service Routines) registere by device drivers for same IRQ line. As mentioned earlieralso, same IRQ line can b shared between different devices, so their device drivers need to register their own ISRs to handle the interrupts genetated by these devices. IRQ descriptor data structure is defined as follows: typedef struct { unsigned int status; hw_irq_controller *handler; struct irqaction *action; unsigned int depth; spinlock_t lock; } ____cacheline_aligned irq_desc_t; Following is the significance of different elements in this stucture: - status : Its a bit mask of different flags to identify the state of a particular IRQ line. We will see the use of differnet flags ahead in this article. - handler : This is the pointer to the structure, whose each element is the pointer to the function related to the handlingof physical PIC (programmable interrupt controller). These functions are used to mask/unmask particular interrup line in PIC or to acknowledge the interrupt to PIC. The definitions of these PIC related functions can be found in file "arch/i386/kernel/i8259.c" - action : This element is the pointer to the list o ISRs registered by different device drivers for this IRQ line. When a device driver registers its ISR to kernel using kernel function "irq_request()", the ISR is added to this list for that particular IRQ line. - lock : This is spinlock to handle the synchronization problem while accessing any element in IRQ descriptor. Kernel execution context access the different elements of IRQ descriptor, but before doing so they should acquire this spinlock so that the synchronization can be maintained. Line - 581 to 583 Here we increment the interrupt count received by this CPU, this is maintained for accounting purpose. Hold the spinlock before accessing any element of the IRQ descriptor for our interrupt line. We also mask and acknowledge the interrupt to PIC using handler function of our IRQ descriptor. Line - 588 to 589 Now we clear the IRQ_REPLAY and IRQ_WAITING flags from ou IRQ descriptor flag. As mentioned earlier this is used to maintain the status of an interrupt handling line. We clear these flags because now we are going to handle this interrupt will not be anymore in reply or waiting mode. Actually IRQ_WAITING flagis used by device drivers in conjunction with IRQ_AUTODETECT flag for auto-detecting the IRQ line to which their device is connected. Device drivers use the probe_irq_on() function, which actually sets he IRQ_AUTODETECT and IRQ_WAITING flag for all the IRQ descriptors for whome no ISR has yet been registered.After calling probe_irq_on() function, device driver instructs the device to trigger an interrupt and then calls probe_irq_off(0 function. probe_irq_off() function actually looks for those IRQ descriptors whose IRQ_AUTODETECT flag is still set butIRQ_WAITING flag has been cleared. and returns the IRQ line number to device driver. After clearing the IRQ_REPLAY and IRQ_WAITING flags in do_IRQ() function we set the IRQ_PENDING function. This is done, to indicate that we are planning to handle this interrupt if this interrupt is not disabled or not bein already handled by another CPU (in case of SMP machines). The use of setting IRQ_PENDING flag is explained in details in next few lines. As we have see the interrupt and want to handle it by calling the set of ISRs (Interrupt Serive Routines) registered by different device drivers. We set IRQ_PENDING flag because seeing an interrupt does not mean we will for sure handle it. IRQ_PENDING flag helps us in following two cases: - In case interrupt is disabled (set flag IRQ_DISABLED), we will not service the interrupt and will just keep it marked as pending (set flag IRQ_PENDING). Once the interrupt is again enabled (clear flag IRQ_DISABLED), ISRs will be called to service the interrupt. So IRQ_PENDING helps us to remember the intterupt which occured while that interrupt was disabled due to some reason. Note: Here disabling interrupt does not mean masking a particular line at PIC level or disabling all the interrupt at CPU level by clearing the IF flag of CPU EFLAG register. Disabling here means the kernel has been asked not to service the interrupt, but the hardware triggering of interrupt signal is not being stopped at all. - In case another CPU is already handling the previous interrupt requests on this IRQ line. In this case flag IRQ_INPROGRESS will already be set by that another CPU. Our role will be to just mark the interrupt as IRQ_PENDING and in away asks that other CPU to service this interrupt request also. When that CPU will finish its handling of previous interrupt, it will check this flag. Because of this flag being set by us, that CPU will again go and call all the ISRs once agian to service interrupt request we received on this IRQ line. Line - 595 to 601 Now we check if this interrupt is not disabled (flag IRQ_DISABLED is clear) and at the same time is also not being handled by another CPU (flag IRQ_INPROGRESS is also clear), we go forward and clear the IRQ_PENDING flag and sets the IRQ_INPROGRESSflag to indicate that we take the responsibility of handling this interrupt request. Now while we are handling this interrupt request, lets sa another CPU receives an interrupt on same IRQ line, that CPU will simple mark the IRQ_PENDING flag and will transfer his responsibility to us and in that case we (CPU we are executing on) will be responsible to serve that interrupt request also. Line - 609 to 610 If there is no registered ISR for this IRQ line, we simply return from interrupt context after releasig the lock we hold and serving the softirqs (if any pending). Line - 622 to 630 Now we are al set to call the registered ISRs (device driver's functions), so that they can figure out which device connected to this IRQ line has actually triggered the interrupt and can serve it poperly. before calling the ISRs, we release the IRQ descriptor spinlock so that while we are executing the ISRs this spinlock can be acquired by another interrupt context, which may execute on another CPU for the same IRQ line. This interrupt context on another CPU will simply mark the IRQ_PENDING flag and return without handling the interrupt itself. In this infite loop we call the handle_IRQ_event() function which actualy calls all the ISRs registrered for this IRQ line one by one. After completing the list of ISRs, we again acquire the IRQdescriptor spinlock as we need to again check and update the flag element of IRQ descriptor. After acquiering the spinlock, we check is the IRQ_PENDING flag is clear, we break out of this infite loop, else we clear the IRQ_PENDING flag of our IRQ descriptor and again go into handle_IRQ_event() function to serve the new interrupt request as indicated by IRQ_PENDING flag. Line - 631 Finally we come out of the above mentioned infite loop only if there is not pending request for thie IRQ line. Once we are out, we are done with the most of the part, so we clear the IRQ_INPROGRESS flag. Line - 637 to 638 Now we call the end function of PIC related functions stored in handler element of our IRQ descriptor. This function take care of the situation where the interrupt we were handling got disabled while we were handling it. Lets sat while we were serving the interrupt by callings all the ISRs for it, the interrupt got disabled (flag IRQ_DISABLED is set) by code running onanother CPU, then in this case we should not unmask the interrupt line (which we masked by calling the PIC related ack() function, line 583). If the IRQ is not yet disabled, this function end() will simply unmask the interrupt line at PIC level and return. After this we go ahead and do serve the pending softirqs (is any marked). We will see in next section what are siftirqs. I will soon post the details of softirqs, tasklets and bottom halfs, so keep looking for that on my blog.

Tags: interrupt, cpu, irq, line, gate