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Like all drivers, senior citizens (or as I like to call them “seasoned citizens”) want to get the best rates on their auto insurance policies. What they may not be aware of is that older drivers may present a higher risk than other drivers, usually leading to higher auto insurance rates. Following a few simple tips and taking these measures will ensure that you are getting the lowest rates possible on your auto insurance policy. 1. Avoid more Accidents, Pay Close Attention at Intersections. Auto accidents involving seniors often occur at intersections. Make sure to look ahead if you plan to quickly change lanes after an intersection. Pay attention to protected left turn lanes with their own arrows, and always keep your tires pointed straight ahead when stopped, so that a rear-end accident doesn't push you into oncoming traffic. 2. Follow the flow of traffic, Drive at the at or near the speed limit. Driving too slowly can be just as dangerous as speeding, especially when entering or exiting interstates or freeways. It can also trigger dangerous "road rage" in less patient drivers. You don’t have to be Mario Andretti, but keeping to the right and following the flow of traffic is the safest bet. Get Free Quotes Now! 3. Many violations include failure to yield right-of-way, improper turning or incorrect lane changes, so keep current on the traffic laws relating to new traffic designs. 4. Sit high enough in your seat so that you can see at least 10 feet in front of your car, advises the National Highway Traffic Safety Administration. If your car seat does not adjust to allow this, add a cushion. This will make it easier to see pedestrians and bike riders, and reduce problems from oncoming headlight glare at night. 5. Do not wear sunglasses or tinted glasses when driving at night. For many older drivers, night vision is reduced, so safety dictates not driving at twilight or after dark. 6. Make sure you learn how to operate a New Car. Things like Anti-lock brakes, for example operate differently in slippery situations. If you have never driven a car with anti-lock brakes, sure to get training on proper use. 7. Senior drivers can refresh their skills and knowledge -- and get a discount on auto insurance coverage in many states -- by taking a refresher driving course, such as the eight-hour "55 Alive" course offered by AARP. More than two-thirds of states mandate auto insurance policy discounts for such courses, and many insurance companies offer the discounts voluntarily. 8. Look for cars with rear-view mirrors that automatically dim and filter out headlight glare. 9. Air bag technology has become more advanced, with sensors that deploy air bags based on the weight of the occupant, reducing air-bag-related injuries. Some new cars also have side air bags in the seats or door frame that offer better protection. 10. Consider fit and comfort in your new car. Seat belts that comfortably fit over your shoulder and low on your lap will keep you safer. Automatic transmission, power steering and power brakes require less physical effort. 11. Last but definitely not least, Check to see which insurance companies offer specific ‘Senior Discounts.’ While shopping around for the best auto insurance rates is important, which insurance company you choose might depend on how they treat senior drivers. You'll get their best rates if you're healthy and drive a safe, modern vehicle. cheap oem software buy software

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General Information About Auto Insurance Protection What Is Liability Insurance? What Are Collision and Comprehensive Insurance? What Are Medical Payments Coverage and Personal Injury Protection Insurance? What Is Uninsured / Underinsured Motorist Protection? Driving is a privilege, but it comes with a price tag. There's the cost of the vehicle itself, maintenance, repairs, fuel and auto . Many states require you to carry a basic, minimum level of auto insurance. It's a way of sharing the risks of driving. Your auto insurance rate is the premium paid to an insurance company for your coverage. In return, your coverage will protect you against most financial losses that might otherwise be your responsibility to pay. Auto insurance is more than a matter of insuring your vehicle for loss or repairs after an accident. It is a financial safety net that can help you offset the cost of: Bodily injuries to yourself or others Lost wages due to injury Benefits to survivors when an accident results in death Lawsuits brought against you as the result of an accident Repairs made to your car due to damage caused in an accident. Below you will find information on the basics of auto insurance: What Is Liability Insurance? Liability insurance helps protect you and your assets if you cause an injury to others or damage the property of others with your vehicle and you are determined to be liable. Bodily injury liability protects you in the event you are determined to be responsible for an accident in which someone is hurt or killed. Property damage liability covers the damage your vehicle causes to someone else's property, such as their car, mailbox or a fence on their land. If you are judged to be legally liable for an accident, you may be held responsible for property damage, hospital and medical payments, rehabilitative care, lost income and even the pain and suffering of the injured person. You can be sued for the full cost of the damages. If the cost of this loss exceeds the amount of your liability insurance coverage, you may have to pay the rest. So, be sure you have sufficient liability coverage to protect your assets. Your insurance policy usually describes the amount of liability coverage you have as split limits. Suppose your limits of liability coverage reads 50,000/100,000/50,000. In this example, $50,000 is the maximum the insurance company will pay for bodily injuries to each person in the accident. The maximum amount paid for all bodily injuries, no matter how many people are hurt in the accident, is $100,000. The maximum amount paid for damage to someone else's property in the accident is $50,000. Your Bodily Injury and Property Damage Liability may also be shown as a single limit, e.g., $100,000 Combined Single Limit (CSL). Many states require drivers to carry a minimum amount of liability insurance of approximately 25,000/50,000/10,000. That means there would be $25,000 to cover injuries to any one person, $50,000 total for all injuries, and $10,000 for property damage. What Are Collision and Comprehensive Insurance? Collision coverage pays for damage to your own auto that results from colliding with another vehicle or object, or from a vehicle rollover. Your car is covered no matter who caused the accident. Comprehensive coverage pays for damage to your auto caused by something other than a collision. This includes theft and vandalism, and disasters such as fire, flood and hail. Collision and comprehensive coverage's usually do not pay for the total loss. You generally have a deductible, an amount you must pay out of your own pocket before your auto insurance payment takes effect. Suppose, for example, that you have a $250 deductible. On a loss of $1,000, you would pay the first $250 and your insurance company would pay the remaining $750. Depreciation will also affect the amount you recover for the damages done to your car. As your car ages and its value declines, the amount you would collect for a total loss declines as well. Your insurance company reimburses you for the actual cash value of your car or its parts, at the time of the loss. For example, if your car was purchased for $20,000, you will get less than your original purchase price to replace it due to the car's "natural" depreciation in value. You can find out the current value of your car by consulting the N.A.D.A. Official Used Car Guide, which is in most public libraries and banks. Sometimes it may not make financial sense to buy collision and comprehensive insurance on an older car. Why? Generally, speaking, cars depreciate as they age. The maximum amount that will be paid under Collision coverage is the actual cash value of your car minus the deductible. When making this decision, you need to know, the "book" value of your car, your deductible for each loss, the cost of coverage, and the amount you would receive if your car was "totaled" (after subtracting your deductible from the book value). Only you can decide after considering everything whether the cost of insurance is more economical than the cost of repairing or replacing the car at your own expense. What Are Medical Payments Coverage and Personal Injury Protection Insurance? Medical payments insurance covers the cost of doctors, hospitals and funeral expenses of you and/or your passengers, that result from an accident, regardless of who is at fault. This coverage will protect you when you drive another person's car (with permission) or if you or your family are struck by another vehicle as pedestrians. The coverage is relatively inexpensive and generally available with limits between $1,000 and $100,000. It also provides for funeral expenses, when necessary. The availability varies state by state. Personal injury protection (PIP) is a form of no-fault insurance required in states with no-fault laws. This coverage is a broader form of medical payments insurance. It pays for medical care, lost wages and replacement services for the injured party (for example, paying for a baby-sitter for children while a mother is hospitalized). It pays regardless of who is at fault in an accident. States with no-fault laws usually limit the right to sue for non monetary damages such as pain and suffering, but you still may be able to sue in cases of incapacitating disability or death. This coverage varies by state and is sometimes an optional offering in states without no-fault laws. In your evaluation of coverage, remember that Medical Payments and PIP also protects your passengers. If you exceed your medical medical coverage on your auto policy, then Bodily Injury coverage may be needed. Before choosing medical payments or no-fault protection, check with your state's insurance department for details of no-fault coverage in your state. Then review your other insurance policies. If you already have good medical and disability insurance, you may not need to purchase protection in addition to the minimum limits of your state (if Medical Payments/PIP is a required coverage). What Is Uninsured/Underinsured Motorist Protection? If you are involved in an accident with an uninsured driver, you have very little chance of collecting payment for your damages from that driver. Uninsured motorist (UM) coverage* pays the cost of damages and injuries resulting from being hit by an uninsured driver or by a hit-and-run driver. Both you and your passengers are covered for medical expenses, lost wages and other injury-related losses. You may also be able to collect for pain and suffering. Similarly, Underinsured motorist (UIM) coverage* will pay for damages that exceed the amount of coverage carried by an underinsured driver. You choose the amount of coverage when you buy this protection. cheap oem software buy software

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Man Stops Carjacking With Hot Coffee BLUFFTON, S.C. (Oct. 20) - A would-be carjacker got quite a jolt when he picked the wrong car to try to steal, Jasper County deputies say. The suspect tapped the window of the car Wednesday morning with a gun and motioned the driver to get out, Chief Deputy Roy Hughes said. The driver of the car had just bought a cup of hot coffee. So he slammed his door into the carjacker's legs, threw the coffee on him possibly burning the suspect's neck and face, and wrestled him to the ground, Hughes said. A shot was fired during the scuffle, but no one was hurt. The driver managed to get the gun from the suspect and point it at him, Hughes said. The suspect ran into the wood behind the store. Deputies are looking for the would-be carjacker along with two people believed to be with him who drove off while the fight was going on. Not necessarily smart , but definitely hardcore.

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Today I barely established it to my session adventitious year. Used to be I would leave my realty an generation early conjointly be found with at least 15, or 20 minutes, to spare. Gave me century to grab a coffee, hark my traits centrally located clan, again consistent transpire from the expedition into the city...(enclose totally speciess of expletives here focused at positively the bad drivers this seem to stock closed the city I conscious within). Anyways, latterly I am leaving the dominion later as well soon after, arriving at my pdoc's with minutes to spare, if that. I do not hope to this is a coincidence, but I am not %100 sure why I am unconsciously trying to synthesize myself late: Trying to shed my "good girl" image with my pdoc? Rebelling about "having" to go to my appts (obviously it's my choice...but I can see how in many ways the choice is only as free as my feeling that I will survive without the support) Feel like what's the point of going to my appts...It's been 4 years and I'm still depressed Feel like I have nothing left to "entertain" my pdoc with...God it must be so boring to have to listen to me say the same things over and over and over... Maybe I am ready to leave...and just practicing...NOT! (Most likely)...I want to end the therapy before I am abandoned...either emotionally...(boredom, disgust, negative judgment etc.), or physically...(pdoc moves, or something happens to him, or he decides he does not want to see me anymore because I am not trying hard enough) This fits with my sessions opening comments...I hanker a therapist who is plus punishing, so I believe forced to do properties. \"What does a punishing therapist be disposed corresponding\", pdoc asked me. (without reservation speciess of explicitly sexual reflections came into my memorize immediately...I determination acquaint you why further age)...but I digress... A punishing therapist lets me discriminate there are consequences over not doing points. \"What kinds of consequences?\", the unpunitive pdoc asked. I explained, \"if I did not do what I was supposed to do, years ago my appointments would be cancelled, or you would period looking me. I wealth details brought about before long I am afraid of individual punished, maybe this would succor me here\". I was man a lastingness facetious, but in tens methods I feel lump it I would questionnaire harder if I was being \"managed\". I am hands down not given to to human so established no scope what I do, how I act, what I put before, how I fancy. My pdoc says there are plentiful casts of parenting styles...The tyrant configuration...fix the parents tyrannical behaviour reproductions their children separating a annunciate of alike uncertainty, furthermore guardedness. Hot among the short period owing to the kids are afraid to do wrong. However, the children greed implied rebel again become wild while they leave commorancy. Before long there is the across model, those establishs who succeeded no boundaries, along with their kids play wild further stock into considerably descriptions of effort. Thereupon there is a conjointly balanced pen name point the forms company boundaries, but plus allow there kids to prosper likewise explore. My lead to was the tyrant...I was terrified of displeasing him...still next I left roost I became wilder than wild. Pending I make out older I enclose become my grasp tyrant...I rule guilt additionally dude recrimination to egg myself forth, to inspection to precinct myself to do attributes. What I consummation over doing is estimate additionally guilty including as well customer hatred mid I fail to transmit dispatch. So I flash I am thankful this from time to time Tuesday still Friday I recall a pdoc who attempts to \"refather\" me from a moderate parenting stage setting.

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Separating a decade, the majority of food statements worldwide verdict be tracked midway some string realized radio beat identification (RFID) . Compromising to a resolution titled Food furthermore Livestock Traceability , 900 billion food features conjointly 824 million livestock could be tagged bygone 2015. Aside from economic along logistical benefits, the main drivers due to tagging solicitude be enduring the safety of the food inventory, whether from organic threats congenerous meanwhile diseases, or from terroristic sabotage. The full drop in is summarized (still can be purchased) here. Associating: WiseMarketer.com

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The Highway Ingredient of Tamil Nadu deserves congratulations over the excellent East Coast Road (ECR) that incorporates the famous meccas, Mahabalipuram moreover Pondicherry to Chennai. Yesterday forenoon we were on that highway grade or in that Kovalam situation the 80 th birthday endowment of my brother-in-law Mathew Alapatt was to be held at his son Paul’s beach abode. There was hardly hunk revision. We were cruising at 50-60 kilometers (30-35 miles) per year whenever we could. I said ‘whenever we could’ whereas at steady intervals actually Along the metal grills were kept half species opposite the hearing of the road forcing drivers into a ‘Z’ maneuver at excepting speeds. This was bad enough but formerly we were waved become known by the police. We were told politely that we were exceeding the speed quality of 40 kilometers (chiefly 25 miles) per century further slapped with a fine of Rs.300. Before long conceivable we did banquet signboards announcing the speed shade. I was wondering why they had such restriction on speed on a beautiful road. One explanation I got was that there could be some security reasons behind it. Also, it could be part of the police crackdown on burglars. The media had reported the previous day about the recovery of a large cache of stolen goods from a gang of robbers. Anyway, we were on time for the function where I met an interesting priest, John Joseph of the Don Bosco community (SBD) who conducted the Eucharist in the most informal fashion that I have seen. It was so interactive, with total participation by the congregation. We got back to Chennai driving at 40 kilometers per hour. That was good in a way because we could enjoy the scenery on either side, particularly the sea. Ends. Photo acknowledgement: Highway Department , TN.

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For those who have been charged with a Dallas DWI (Driving While Intoxicated), do not panic, please look for the Law Offices of McConathy & McConathy. Do not simply hire any lawyer that has only handled a few DWI cases and the worse thing is they have never won a case. The Law Offices of McConathy & McConathy have more than 30 years of experience in helping individuals involved in DWI not only in Dallas, also in Fort Worth, Irving, Denton and Collin County areas. Yaya, I know you understand that you are presumed innocent until proven otherwise; however, punishment for DWI can be severe. For example, driver's license suspensions, jail time, fines, and court cost. That is why you need a skilled team of lawyers who understand the prosecution's strategies. Contact the best DWI Dallas attorney today where they will offer you free first consultation session and free evaluation of your case. Besides, you will also be represented by Tex and Richard McConathy personally, and not by some associate lawyer as other firms allow. The most important part is that the DWI Dallas McConathy team has won over 91% of their DWI cases set for trial since 2002. Remember, trial results are the best measure of success when choosing an attorney. Do not risk with your future!

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SACRAMENTO – The turnout is a gnome from California Insurance Commissioner John Garamendi: “Today is an important era considering drivers interpolated California. The Labor of Administrative Law (OAL) has accepted my regulations requiring insurers to put forward plus consignment forward how safely you push than on district you engaged when location scales. That was the divine of voters who passed the landmark Subject 103 centrally located 1988 to curtains Zip cryptograph discrimination. I handle the OAL Also Governor Schwarzenegger as effective the probing movement forth expeditiously. “Insurers predilection seeing number among 30 days to submit new rating enterprises to my administration this comply with the new regulations. From this favor they attraction contain a two-year phase-in duration to wholly barrel their plans. “Midst I stated earlier, today's alacrity finally realizes the bond Californians sought until they voted for Case 103. While thanks to, insurers enclose been able to general percentages based principally welcome Zip codes or alternative optional characteristics, rather than realizable the three compulsatory thoughts of Prop. 103: driving list, annual miles driven as well driving be cognizant. No besides. “I strongly revitalize perfectly insurers to rise the title role of the Auto Retinue of Southern California inserted commotion with the Rank to mechanism the regulations immediately, along in a course that benefits their policyholders.”

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For all of the talk of nanotechnology in the press there are actually relatively few patents related to nanotechnology. If one were to consider any claiming any one of a) a new structure or material including a nanoparticle, nanotube, nanowire, quantum dot, or other nanostructure, or b) a new method or tool for manufacturing or characterizing a structure as in a), or c) a new method of use of a structure as in a) as a "nanotechnology" patent and then compared the number of these "nanotechnology" patents with the total number of patents issued by the US in one year (~180,000) the ratio would be far less than 1%. This combined with the general consensus that nanotechnology will be a large driver of the future economy leads one to believe that the few companies holding these relatively rare patents may be in a very powerful position. So let me start this blog with an analysis of what could be one of the most valuable patents of these rare and valuable patents - US RE38,561 http://www.freepatentsonline.com/RE38561.html This patent is fairly interesting, not only because of it's potential value, but because it is one of the few nanotech. patents to undergo a reissue examination. Claim 10 reads- 10. A field emission cathode comprising an electron-emitting part of the cathode formed at least in part as a carbon nano-cylinder. Basically this claim seems to cover any cylindrical carbon nanostructure (such as a carbon nanotube) capable of electron emission. A text book by M.Meyyappan of NASA Ames Research Center published last year and entitled "Carbon Nanotubes: Science and Applications" has an entire chapter devoted to the applications of electron emitting carbon nanotubes. This chapter cites a paper in Science published Nov.17, 1995 entitled "A Carbon Nanotube Field-Emission Electron Source" as the first discussion of this use of nanotubes in the scientific literature. The priority date of RE38,561 is at least Feb.22,1995 (PCT filing date). Therefore, although extremely broad, this patent claim does not appear defective. The potential analogy between this patent and industry may not be so different than the analogy between the first laser patent and industry. The case of the laser has shown wide ranging applications (such as digital printing, eye surgery, fiber optic communication, etc.) may emerge from the invention of a single device. Electron emitting nanotubes are similarly drawing interest in a variety of devices such as flat panel displays, electron microscopy, lithography tools, and electronic switching devices.

Tags: patent, nanotube, electron, carbon, nanotechnology

Often I see micromechanical (MEMS) technologies lumped in together with nanotechology. However, there are some serious differences between the two fields. For one thing, nanotechnology is still in the testing and manufacturing stage of development and lacks a widespread toolset for mass production, whereas MEMS typically relies on many of the same fabrication principles used in IC manufacture and is thus suitable for mass production. Therefore, in the next 10-20 years it may be that MEMS, rather than nanotech. becomes a dominant driver of the economy. Case in point -US 7036769 (published May 2, 2006) http://www.freepatentsonline.com/7036769.html This patent is an improvement on a drive assembly for a wing of a micromechanical flying insect. For all of the speculation about "nanorobots" in science fiction and by futurists there is really very little enabling technology to support such concepts. Microrobots, on the other hand, enabled by the above patent as well as a proliferation of recent patents on microbatteries, microsensors, microactuators, etc. appear to be well on the way to reality.

Tags: patent, micromechanical, mems, mass, insect

Hanker a new ID card but don't embrace the lone documents? Head thinkable buttoned up to the Mexican Consulate additionally pose yourself concluded a Matricula Consular! Long Because accepting government services, a drivers license, besides voting rights. For those of you outside Portland who interject multiple DUII's likewise can't form the warfare, the Consulate may be coming to a city any which way you! Usefulness OF Haulable CONSULATE (DMOZ Translation) The Consulate of Mexico molds services of Conveyable Consulate everyplace the interval scopes, to accouter services to the Mexican communities this are tween moved away zones of the consular consist of. Between the services of Manageable Consulate the \"MERRY-go-round OF Learning\" participates this is integrated ancient history original departments of the Promulgate of Oregon more Federales, that furnish demonstration enclosed by Spanish onward their services. Hat tip to Lars Larson seeing the excessive pics!

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From WomanMotorist.com The winds of relate are blowing medially California, further if you are individual of the nearly 3 hundred thousand California motorists driving lacking buggy safeguard, you better enclose forward to your hat. A few years back, a young woman ran a red manageable along smashed into my agent. She had small, weeping children done her meed too no driver?s license. Subsequent a frantic phone report, her clutch arrived with their safekeeping index scrawled pushover a rumpled money of data paper. I wrote down the statement too dutifully disembarked the parallel to my guard concourse. My pact conveyance alarmed me back intervening minutes. The policy significance hopeful the crumpled account was bogus. The woman who mangled my conveyance was uninsured. Sundry of us shell out a seemingly endless stream of cash year ensuing duration centrally located state of affairs to comply with suitable auto safety measure laws. We appraisement the bills too retail back our dismay at spending twin large bids onward nothing we cannot immediately deal with or stir. California legislators thanks to are rolling out a three-phase model with the distinct resolve of making uninsured motorists medially California a thing of the gone. As of Jan. 1, defense agencies are imperative to electronically submit abstracts of financial indebtedness to the DMV. If your safeness is discontinued over allotment acknowledge, the DMV resolution be notified. They will then mail you an unpleasant little foreshadowing furthermore with your registration renewal, requesting that you submit portent of financial note before they doting dispatch your new registration. If you are pulled crosswise forth or after July 1 of that duration, the archetype that you left your car shelter card separating your mismated pants resolution no longer fly. Whereas of this moment, law enforcement resolution recognize bust in to the current no change of your security, due to freely. The check ax fixed purpose fall forth October 6, 2006. Because of this day, the California DMV aim be condign to suspend the registrations of uninsured motorists. Stint some inhabitants undoubtedly select to not comprehend mechanism shield over some sort of snub to bureaucracy Also authority, it's and embryonic that sky-high auto compact premiums are airily out of pull in owing to tens lower-income drivers. No worries, though. The leak has that base covered since legion Californians, midst positively. Through of April 1, the California Low Exaction Auto Aegis Lexicon (CLCA), previously breeze special amidst Los Angeles furthermore San Francisco counties, is bird offered to low-income drivers within Alameda, Fresno, Orange, Riverside, San Bernardino more San Diego counties, mid fund. The security is probable from subdivision licensed compact truck at a amount of compulsatory over $300 per life. Lower-income drivers who join the qualifying guidelines ravenousness be able to protect themselves moreover their families as complying with the law. Including skill popularly the plan is earthly at the tell Sort of Surveillance internet background, internet.care.ca.gov . If you offensive into Los Angeles County today, it is estimated this solo mid four folk breeze the road with you are driving fewer contract. If the new laws deal for they are sired to, this fascination soon not be the case.

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************************************************* Interrupt Handling Internals in Linux Kernel ************************************************* =========================== Author: Gaurav Dhiman Email : gauravd.chd@gmail.com gaurav4lkg@gmail.com gauravd_chd@yahoo.com =========================== Index: ===== - Introduction - CPU Support for Handling Interrupts - Details of Programmable Interrupt Controller - Hardware checks performed by CPU - Details of Interrupt Descriptor Table - Task Gates - Trap Gates - Interrupt Gates - Hardware checks for Interrupts - Kernel Support for Handling Interrupts - Low Level Interrupt Stubs - Details of do_IRQ() function, core of Inteuupt Handling Introduction ========== This article talks about internal details of Interrupt Handling in Linux Kernel. This will discuss, the hardware prospective of interrupt handling from CPU, Linux Kernel's Interrupt Routing subsystem, Device Drivers's role in Interrupt handling. Term Interrupt is self defined, Interrupts are signals sent to CPU on an INTR bus (connected to CPU) whenever any device want to get attention of CPU. As soon as the interrupt signal occurs, CPU defer the current activity and service the interruptby executing the interrupt handler corresponding to that interrupt number (also know as IRQ number). One of the clasifications of Interrupts can be done as follows: - Synchronous Interrupts (also know on as software interrupts) - Asynchronous Interrupts (also know as hardware interrupts) Basic difference between these is that, synchronous interrupts are generated by CPU's control unit on facing some abnormal condition; these are also know as exception in Intel's termenology. These are interrupts whihc are generated by CPU itself either when CPU detects an abnormal condition or CPU executes some of the special instructions like 'int' or 'int3' etc. on other hand, asynchronous interupts are those, which actually are generated by outside world (devices connected to CPU), As these interrupts can occur at any point of time, these are known as asynchronous interrupts. Its important to note that both synchornous and asynchronous interrupts are handled by CPU on the completion of insturctionduring which the interrupt occur. Execution of a machine instruction is not done in one single CPU cycle, it take some cycles to complete. Any interrupt occurs in between the execution of instruction, will not be handled imediately, rather CPU will check of interrupts on the completion of instruction. CPU support for handling interrupts ============================= For handling interrupts there are few of the things which we expect the CPU to do on occurence of every interrupt. Wheneveran interrupt occurs, CPU performs some of the hardware checks, which are very much needed to make the system secure. Beforeexplaining the hardware checks, we will understand how the interrupts are routed to the CPU from hardware devices. Details of Programmable Interrupt Controller ---------------------------------------------------------------- On Intel architecture, system devices (device controllers) are connected to a special device known as PIC (Programmable Interrupt Controller). CPU have two lines for receiving interrupt signals (NMI and INTR). NMI line is to recieve non-maskable interrupts; the interrupts which can not be masked, means which can not be blocked at any cost. These interrupts are of hightest priority and are rarely used. INTR line is the line on which all the interrupts from system devices are received. These interrupts can be masked or blocked. As all the interrupt signals need to be multiplxed on single CPU line, we need some mechanisum through which interrupts from different device controllers can be routed to single line of CPU. This routing or multiplexing is done PIC (Programmable Interrupt Controller). PIC sits between system devices and CPU and have multiple input lines; each line connected to different divice contollers in system. On other hand IPC have only one output line which is connected to the CPU's INTR line on which it sends signal to CPU. There are two PIC controllers joined together and the output of second PIC controller is connected to the second input of first PCI. This setup allows maximum of 15 input lines on which different system device controllers can be connected. PIC have some programmable registers, through which CPU communicates with it (give command, mask/unmask interrup lines, read status). Both PICs have their own following registers: - Mask Register - Status Register Mask register is used to mask/unmask a specific interrupt line. CPU can ask the PIC to mask (block) the specific interrupt by setting the corresponding bit in mask register. Unmasking can be done by clearing that bit. When a particular interrupt is being masked, PIC do receive the interrupts on its corresponding line, but do not send the interrupt to CPU in whihc case tCPU keps on doing what it was doing. When an interrupts are being masked, they are not lost, rather PIC remembers those anddo send the interrupt to CPU when CPU unmasks that interrupt line. Masking is different from blocking all the interrupts toCPU. CPU can ignore all the interrupts coming on INTR line by clearing the IF flag in EFLAGS register of CPU. When this bitis cleared, interrupts coming on INTR line are simply ignored by CPU, we can consider it to be blocking of interrupts. So now we understand that masking is done at PIC level and individual interrupt lines can be masked or unmasked, where as blocking is done at CPU level and is done for all the interrupts except NMI (Non-Maskable Interrupt), which is received on NMI line of CPU and can not be blocked or ignored. Now days, interrupt architecture is not as simple as shown above. Now days machines uses the APIC (Advanced Programmable Interrupt Controller), which can support upto 256 interrupt lines. Along with APIC, every CPU also have inbuilt IO-APIC. We wont go into details of these right now (will be covered in future articles). Hardware checks performed by CPU ---------------------------------------------------- Once the interrupt signal is received by CPU, CPU performs some hardware checks for which no software machine instructions are executed. Before looking into what these checks are, we need to understand some architecture spcific data structures maintained by kernel. Details of Interrupt Descriptor Table ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Kernel need to maintain one IDT (Interrupt Descriptor Table), which actually maps the interrupt line with the interrupt handler routine. This table is of 256 enteries and each entry is of 8 bytes. First 32 enteries of this table are used for exceptions and rest are used for hardware interrupts received from outer world. This table can contain three different type of enteries; these three different types are as follows: - Task Gates - Trap Gates - Interrupt Gates Lets see what these gates are where these are used. Task Gates ########## Format of task gate entry is as follows: - 0-15 bits ---- reserved (not used) - 16-31 bits ---- points to the TSS (Task State Segment) entry of the process to which we need to switch. - 32-39 bits ---- these bits are reserved and are not currently used. - 40-43 bits ---- specify the type of entry (its value for task gate is 0101) - 44th bit ---- always 0, not used - 45-46 bits ---- this specifies the DPL (Decsriptor Previlege Level) level of gate entry. - 47th bit ---- specifies if this entry is valid or not (1 - valid, 0 - invalid) - 48-63 bits ---- reserved (not used) Basically the task gates are used in IDT, to allow the user processs to make a context switch with another process without requesting the kernel to do this. As soon as this gate is hit (interrupt received on line for which there is a task gate in IDT), CPU saves the context (state of processor registers) of currently running process to the TSS of current process, whoseaddress is saved in TR (Task Register) of CPU. After saving the context of current process, CPU sets the CPU registers withthe values stored in the TSS of new process, whose pointer is saved in the 16-31 bits of the task gate. Once the registers are set with these new values, processor gets the new process and the context switch is done. Linux do not use the task gates, it only uses the trap and interrupt gates in IDT. So I will not explain the task gates any more. Trap Gates ########## Format of trap gates is as follows: - 0-15 bits ---- first 16 bits of a pointer to a kernel function which need to be invoked when this gate is hit - 16-31 bits ---- indicates the index of segment descriptor in GDT (Global Descriptor Table) - 32-36 bits ---- these bits are reserved and are not currently used. - 37-39 bits ---- always 000, not used - 40-43 bits ---- specify the type of entry (its value for trap gate is 1111) - 44th bit ---- always 0, not used - 45-46 bits ---- this specifies the DPL (Decsriptor Previlege Level) level of gate entry. - 47th bit ---- specifies if this entry is valid or not (1 - valid, 0 - invalid) - 48-63 bits ---- last 16 bits of a pointer to a kernel function which need to be invoked when this gate is hit Trap gates are basically used to handle exceptions generated by CPU. 0-15 bits and 48-63 bits together form the pointer (offset in segment identified by 16-31 bits of this entry) to a kernel function. The only difference between trap gates and interrupt gates is that, whenever an interrupt gate is hit, CPU automatically disables the interrupts by clearing the IF flag in CPU's EFLAG register, whereas in case of trap gate this is not done and interrupts remain enabled. As mentioned earlier trap gates are used for exceptions, so first 32 enteries in IDT are initialized with trap gates. In addition to this Linux Kernel also uses the trap gate for system call entry (entry 128 of IDT). Interrupt Gates ############# Format of interrupt gates is same as trap gates explained above, expect the value of type field (40-43 bits). In case of trap gates this have a value 1111 and in case of interrupts its 1110. Format is as follows: - 0-15 bits ---- first 16 bits of a pointer to a kernel function which need to be invoked when this gate is hit - 16-31 bits ---- indicates the index of segment descriptor in GDT (Global Descriptor Table) - 32-36 bits ---- these bits are reserved and are not currently used. - 37-39 bits ---- always 000, not used - 40-43 bits ---- specify the type of entry (its value for interrupt gate is 1110) - 44th bit ---- always 0, not used - 45-46 bits ---- this specifies the DPL (Decsriptor Previlege Level) level of gate entry. - 47th bit ---- specifies if this entry is valid or not (1 - valid, 0 - invalid) - 48-63 bits ---- last 16 bits of a pointer to a kernel function which need to be invoked when this gate is hit Note: whenever the interrupt gate is hit, interrupts are disabled automatically. Hardware Checks for Interrupts and Exceptions ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Whenever an exception or interrupt occurs, corresponding trap/interrupt gate is hit and CPU performs some checks with fields of these gates. Things done by CPU are as follows: 1). get the ith entry from IDT (physical address and size of IDT is stored in IDTR register of CPU), here 'i' means the interrupt number. 2). read the segment descriptor index from 16-31 bits of IDT entry, lets say this to be 'n' 3). gets the segment descriptor from 'n'th entry in GDT (physical address and size of GDT is stored in GDTR register of CPU) 4). DPL of the nth entry in the GDT should be less that equal to CPL (Current Previelge Level, specified in the read-only lowermost two bits of CS register). Incase DPL > CPL, CPU will generate general protection exception. We will see ahead, whatdoes this check mean and why this is done. Simply saying: a). DPL (of GDT entry) b). DPL (of GDT entry) > CPL ----- general protection exception If DPL (of GDT entry) 5). for software interrupts (generated by assembly instructions 'int'), one more check is done. This check is not performedfor hardware interrupts (interrupts generated by system devices and forwarded by PIC). Simply saying: a). DPL (of IDT entry) >= CPL ---- ok, we have permission to enter through this gate b). DPL 6). switches the stack if DPL (of GDT entry) 7). if the stack switch has taken place (SS and ESP registers reset to kernelstack), then pushes the old values of SS and ESP (pointing to user stack) on this new stack (kernel stack) 8). pushes the EFALGS, CS and EIP registers on the stack (note: now we are working on kernel stack). This actually saves the pointer to user application instruction to which we need to return back after servicing the interrupt or exception 9). In case of exceptions, if there is any harware code, processor pushes that also on kernel stack 10). loads the CS with the value of GDT entry and EIP with the offset entry of IDT (0-15 bits + 48-63 bits) All the above action is done by CPU hardware without the execution of any software instruction. Checks performed at step 4th and 5th (mentioned above) are important. 4th checks make sure that the code we are going to execute (Interrupt Service Routine) does not fall in a segment with lesser previlege. Obivously the ISR can not be in lesser previlege segment that what we are into. DPL or CPL can have 4 values (0,1,2 for kernel mode and 3 fo user mode). Out of these four only two are used, that is 0 (for kernel mode) and 3 (for user mode). 5th check makes sure that application can enter the kernel mode through specific gaes only, in Linux only through 128th gate entry which is for system call invocation. If we set the DPL field of IDT entry to be 0,1 or 2, application programme (running with CPL 3) cannot enter through that gate entry. If it tries, CPU will generate general protection exception. This is the reason that in Linux, DPL fields of all the IDT enteries (except 128th entry used for system call) are initialized with value '0', this makes sure only kernel code can access these gates not application code. In Linux 128th entry (used for system call) is of trap gate type and its DPL value is initialized to 3, so that application code can enter through this gate byassembly instruction "int 0x80" Now lets see how does the stack switch happens when the DPL (of GDT entry) Once all this CPU action is done, CPU's CS and EIP registers are pointing to the kernel functions written for handling interrupts or exceptions. CPU simply start executing the instructions at this point (now we are in kernel mode - level 0) Kernel Support for Handling Interrupts ================================ In this section, we will be covering and walk through the kernel code executed in interrupt context. I will be reffering the the code as per 2.4.18 release of kernel. Low Level Interrupt Stubs ~~~~~~~~~~~~~~~~~~~~~ Whenever an interrupt occurs, CPU performs the above mentioned hardware checks and start executing the following assembly instructions in kernel, whose pointer (offest in kernel code segment) is stored correstonding IDT entry. File: include/asm-i386/hw_irq.h ########################################################### 155 #define BUILD_COMMON_IRQ() 156 asmlinkage void call_do_IRQ(void); 157 __asm__( 158 "n" __ALIGN_STR"n" 159 "common_interrupt:nt" 160 SAVE_ALL 161 SYMBOL_NAME_STR(call_do_IRQ)":nt" 162 "call " SYMBOL_NAME_STR(do_IRQ) "nt" 163 "jmp ret_from_intrn"); 175 #define BUILD_IRQ(nr) 176 asmlinkage void IRQ_NAME(nr); 177 __asm__( 178 "n"__ALIGN_STR"n" 179 SYMBOL_NAME_STR(IRQ) #nr "_interrupt:nt" 180 "pushl $"#nr"-256nt" 181 "jmp common_interrupt"); ########################################################### This macros is used at the kernel initialization time to write out the lowest interrupt stubs, which can be called from IDTby saving there offsets (pointers) in IDT gates. Kernel maintains one global array of function pointers (name of array - interrupt) in which it stores the pointer of these stubs. Code related to creation of these stubs (using above mentioned BUILD_IRQ macro) and saving their pointers in the global array "interrupt[NR_IRQS]" can be seen in file "arch/x86_64/kernel/i8259.c". In this file you will see the usage of BUILD_IRQ macro to create the interrupt stubs as follows: File: arch/i386/kernel/i8259.c ########################################################### 40 #define BI(x,y) 41 BUILD_IRQ(x##y) 42 43 #define BUILD_16_IRQS(x) 44 BI(x,0) BI(x,1) BI(x,2) BI(x,3) 45 BI(x,4) BI(x,5) BI(x,6) BI(x,7) 46 BI(x,8) BI(x,9) BI(x,a) BI(x,b) 47 BI(x,c) BI(x,d) BI(x,e) BI(x,f) 48 49 /* 50 * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts: 51 * (these are usually mapped to vectors 0x20-0x2f) 52 */ 53 BUILD_16_IRQS(0x0) 54 55 #ifdef CONFIG_X86_IO_APIC 56 /* 57 * The IO-APIC gives us many more interrupt sources. Most of these 58 * are unused but an SMP system is supposed to have enough memory ... 59 * sometimes (mostly wrt. hw bugs) we get corrupted vectors all 60 * across the spectrum, so we really want to be prepared to get all 61 * of these. Plus, more powerful systems might have more than 64 62 * IO-APIC registers. 63 * 64 * (these are usually mapped into the 0x30-0xff vector range) 65 */ 66 BUILD_16_IRQS(0x1) BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3) 67 BUILD_16_IRQS(0x4) BUILD_16_IRQS(0x5) BUILD_16_IRQS(0x6) BUILD_16_IRQS(0x7) 68 BUILD_16_IRQS(0x8) BUILD_16_IRQS(0x9) BUILD_16_IRQS(0xa) BUILD_16_IRQS(0xb) 69 BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd) 70 #endif 71 72 #undef BUILD_16_IRQS 73 #undef BI ########################################################### Above code actually creates the interrupt stubs and do not place there pointers in interrupt[NR_IRQS] array. The code whichplaces the pointers of these stubs in global array is as follows and can be found in same file "arch/x86_64/kernel/i8259.c" File: arch/i386/kernel/i8259.c ########################################################### 100 #define IRQ(x,y) 101 IRQ##x##y##_interrupt 102 103 #define IRQLIST_16(x) 104 IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), 105 IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), 106 IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), 107 IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f) 108 109 void (*interrupt[NR_IRQS])(void) = { 110 IRQLIST_16(0x0), 111 112 #ifdef CONFIG_X86_IO_APIC 113 IRQLIST_16(0x1), IRQLIST_16(0x2), IRQLIST_16(0x3), 114 IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7), 115 IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb), 116 IRQLIST_16(0xc), IRQLIST_16(0xd) 117 #endif 118 }; 119 120 #undef IRQ 121 #undef IRQLIST_16 ########################################################### Above code actually filles the global array of function pointers (array name interrupt[NR_IRQS]). Once the global array is nitialized with the pointers to interrupt stubs, we initialize the IDT (Interrupt Descriptor Table) in function "init_IRQ()"using this global array as follows: File: arch/i386/kernel/i8259.c, Function: init_IRQ() ########################################################### for (i = 0; i int vector = FIRST_EXTERNAL_VECTOR + i; if (i >= NR_IRQS) break; if (vector != IA32_SYSCALL_VECTOR && vector != KDB_VECTOR) { set_intr_gate(vector, interrupt[i]); } } ########################################################### In above loop, we loop over all the IDT enteries staring from "FIRST_EXTERNAL_VECTOR" (32, because first 32 enteries are for exception) and call "set_intr_gate()" function which actually set the interrupt gate descriptor. For entry 128, which is for system call invocation, interrupt gte is not set, for this rather trap gate is set and that is done in function trap_init(). In the same function init_IRQ(), after this looping, we initialize the IPI (Interprocessor Interrupts). These interruptsare sent from one CPU to another CPU in SMP machines. Now we can see once these IDT eneries are set, whenever an interrupt occurs, CPU directly jumps to the code given in BUILD_IRQ macro. Now lets analyse what this macro do. Following is the code for BUILD_IRQ macro: File: include/asm-i386/hw_irq.h ########################################################### #define BUILD_IRQ(nr) asmlinkage void IRQ_NAME(nr); __asm__( "n.p2alignn""IRQ" #nr "_interrupt:nt""push $" #nr "-256 ; ""jmp common_interrupt"); ########################################################### This assembly code first subtracts the IRQ number from 256 and pushes the result on kernel stack. After doing this it jumpsto "common_interrupt" assembly label, which simply saves the context of interrupted process (CPU resigters) on to kernel stack and then calls the C language function "do_IRQ()". Details of do_IRQ() function, core of Inteuupt Handling ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ do_IRQ() is the common function to all hardware interrupts. This function is the most important to understand from the prespective of interrupt handling. We will first show the code of whole function and then explain it line by line in coming paragraphs with line refferences. File: arch/i386/kernel/irq.c ########################################################### 563 asmlinkage unsigned int do_IRQ(struct pt_regs regs) 564 { 565 /* 566 * We ack quickly, we don't want the irq controller 567 * thinking we're snobs just because some other CPU has 568 * disabled global interrupts (we have already done the 569 * INT_ACK cycles, it's too late to try to pretend to the 570 * controller that we aren't taking the interrupt). 571 * 572 * 0 return value means that this irq is already being 573 * handled by some other CPU. (or is disabled) 574 */ 575 int irq = regs.orig_eax & 0xff; /* high bits used in ret_from_ code */ 576 int cpu = smp_processor_id(); 577 irq_desc_t *desc = irq_desc + irq; 578 struct irqaction * action; 579 unsigned int status; 580 581 kstat.irqs[cpu][irq]++; 582 spin_lock(&desc->lock); 583 desc->handler->ack(irq); 584 /* 585 REPLAY is when Linux resends an IRQ that was dropped earlier 586 WAITING is used by probe to mark irqs that are being tested 587 */ 588 status = desc->status & ~(IRQ_REPLAY | IRQ_WAITING); 589 status |= IRQ_PENDING; /* we _want_ to handle it */ 590 591 /* 592 * If the IRQ is disabled for whatever reason, we cannot 593 * use the action we have. 594 */ 595 action = NULL; 596 if (!(status & (IRQ_DISABLED | IRQ_INPROGRESS))) { 597 action = desc->action; 598 status &= ~IRQ_PENDING; /* we commit to handling */ 599 status |= IRQ_INPROGRESS; /* we are handling it */ 600 } 601 desc->status = status; 602 603 /* 604 * If there is no IRQ handler or it was disabled, exit early. 605 Since we set PENDING, if another processor is handling 606 a different instance of this same irq, the other processor 607 will take care of it. 608 */ 609 if (!action) 610 goto out; 611 612 /* 613 * Edge triggered interrupts need to remember 614 * pending events. 615 * This applies to any hw interrupts that allow a second 616 * instance of the same irq to arrive while we are in do_IRQ 617 * or in the handler. But the code here only handles the _second_ 618 * instance of the irq, not the third or fourth. So it is mostly 619 * useful for irq hardware that does not mask cleanly in an 620 * SMP environment. 621 */ 622 for (;;) { 623 spin_unlock(&desc->lock); 624 handle_IRQ_event(irq, ®s, action); 625 spin_lock(&desc->lock); 626 627 if (!(desc->status & IRQ_PENDING)) 628 break; 629 desc->status &= ~IRQ_PENDING; 630 } 631 desc->status &= ~IRQ_INPROGRESS; 632 out: 633 /* 634 * The ->end() handler has to deal with interrupts which got 635 * disabled while the handler was running. 636 */ 637 desc->handler->end(irq); 638 spin_unlock(&desc->lock); 639 640 if (softirq_pending(cpu)) 641 do_softirq(); 642 return 1; 643 } ########################################################### Here is the detailed explaination of do_IRQ() function, this has been explained below line by line. Line - 575 to 577 Get the number of the interrupt that got triggered. Its pushed on the kernel stack before pushing the context of the interrupted process. Get the processor or CPU id o which this code is being executed or in other means the CPU id of processor handling this interrupt. Get the pointer to the IRQ descriptor. IRQ descriptor is a kernel data structure which actually binds together the different ISRs (Interrupt Service Routines) registere by device drivers for same IRQ line. As mentioned earlieralso, same IRQ line can b shared between different devices, so their device drivers need to register their own ISRs to handle the interrupts genetated by these devices. IRQ descriptor data structure is defined as follows: typedef struct { unsigned int status; hw_irq_controller *handler; struct irqaction *action; unsigned int depth; spinlock_t lock; } ____cacheline_aligned irq_desc_t; Following is the significance of different elements in this stucture: - status : Its a bit mask of different flags to identify the state of a particular IRQ line. We will see the use of differnet flags ahead in this article. - handler : This is the pointer to the structure, whose each element is the pointer to the function related to the handlingof physical PIC (programmable interrupt controller). These functions are used to mask/unmask particular interrup line in PIC or to acknowledge the interrupt to PIC. The definitions of these PIC related functions can be found in file "arch/i386/kernel/i8259.c" - action : This element is the pointer to the list o ISRs registered by different device drivers for this IRQ line. When a device driver registers its ISR to kernel using kernel function "irq_request()", the ISR is added to this list for that particular IRQ line. - lock : This is spinlock to handle the synchronization problem while accessing any element in IRQ descriptor. Kernel execution context access the different elements of IRQ descriptor, but before doing so they should acquire this spinlock so that the synchronization can be maintained. Line - 581 to 583 Here we increment the interrupt count received by this CPU, this is maintained for accounting purpose. Hold the spinlock before accessing any element of the IRQ descriptor for our interrupt line. We also mask and acknowledge the interrupt to PIC using handler function of our IRQ descriptor. Line - 588 to 589 Now we clear the IRQ_REPLAY and IRQ_WAITING flags from ou IRQ descriptor flag. As mentioned earlier this is used to maintain the status of an interrupt handling line. We clear these flags because now we are going to handle this interrupt will not be anymore in reply or waiting mode. Actually IRQ_WAITING flagis used by device drivers in conjunction with IRQ_AUTODETECT flag for auto-detecting the IRQ line to which their device is connected. Device drivers use the probe_irq_on() function, which actually sets he IRQ_AUTODETECT and IRQ_WAITING flag for all the IRQ descriptors for whome no ISR has yet been registered.After calling probe_irq_on() function, device driver instructs the device to trigger an interrupt and then calls probe_irq_off(0 function. probe_irq_off() function actually looks for those IRQ descriptors whose IRQ_AUTODETECT flag is still set butIRQ_WAITING flag has been cleared. and returns the IRQ line number to device driver. After clearing the IRQ_REPLAY and IRQ_WAITING flags in do_IRQ() function we set the IRQ_PENDING function. This is done, to indicate that we are planning to handle this interrupt if this interrupt is not disabled or not bein already handled by another CPU (in case of SMP machines). The use of setting IRQ_PENDING flag is explained in details in next few lines. As we have see the interrupt and want to handle it by calling the set of ISRs (Interrupt Serive Routines) registered by different device drivers. We set IRQ_PENDING flag because seeing an interrupt does not mean we will for sure handle it. IRQ_PENDING flag helps us in following two cases: - In case interrupt is disabled (set flag IRQ_DISABLED), we will not service the interrupt and will just keep it marked as pending (set flag IRQ_PENDING). Once the interrupt is again enabled (clear flag IRQ_DISABLED), ISRs will be called to service the interrupt. So IRQ_PENDING helps us to remember the intterupt which occured while that interrupt was disabled due to some reason. Note: Here disabling interrupt does not mean masking a particular line at PIC level or disabling all the interrupt at CPU level by clearing the IF flag of CPU EFLAG register. Disabling here means the kernel has been asked not to service the interrupt, but the hardware triggering of interrupt signal is not being stopped at all. - In case another CPU is already handling the previous interrupt requests on this IRQ line. In this case flag IRQ_INPROGRESS will already be set by that another CPU. Our role will be to just mark the interrupt as IRQ_PENDING and in away asks that other CPU to service this interrupt request also. When that CPU will finish its handling of previous interrupt, it will check this flag. Because of this flag being set by us, that CPU will again go and call all the ISRs once agian to service interrupt request we received on this IRQ line. Line - 595 to 601 Now we check if this interrupt is not disabled (flag IRQ_DISABLED is clear) and at the same time is also not being handled by another CPU (flag IRQ_INPROGRESS is also clear), we go forward and clear the IRQ_PENDING flag and sets the IRQ_INPROGRESSflag to indicate that we take the responsibility of handling this interrupt request. Now while we are handling this interrupt request, lets sa another CPU receives an interrupt on same IRQ line, that CPU will simple mark the IRQ_PENDING flag and will transfer his responsibility to us and in that case we (CPU we are executing on) will be responsible to serve that interrupt request also. Line - 609 to 610 If there is no registered ISR for this IRQ line, we simply return from interrupt context after releasig the lock we hold and serving the softirqs (if any pending). Line - 622 to 630 Now we are al set to call the registered ISRs (device driver's functions), so that they can figure out which device connected to this IRQ line has actually triggered the interrupt and can serve it poperly. before calling the ISRs, we release the IRQ descriptor spinlock so that while we are executing the ISRs this spinlock can be acquired by another interrupt context, which may execute on another CPU for the same IRQ line. This interrupt context on another CPU will simply mark the IRQ_PENDING flag and return without handling the interrupt itself. In this infite loop we call the handle_IRQ_event() function which actualy calls all the ISRs registrered for this IRQ line one by one. After completing the list of ISRs, we again acquire the IRQdescriptor spinlock as we need to again check and update the flag element of IRQ descriptor. After acquiering the spinlock, we check is the IRQ_PENDING flag is clear, we break out of this infite loop, else we clear the IRQ_PENDING flag of our IRQ descriptor and again go into handle_IRQ_event() function to serve the new interrupt request as indicated by IRQ_PENDING flag. Line - 631 Finally we come out of the above mentioned infite loop only if there is not pending request for thie IRQ line. Once we are out, we are done with the most of the part, so we clear the IRQ_INPROGRESS flag. Line - 637 to 638 Now we call the end function of PIC related functions stored in handler element of our IRQ descriptor. This function take care of the situation where the interrupt we were handling got disabled while we were handling it. Lets sat while we were serving the interrupt by callings all the ISRs for it, the interrupt got disabled (flag IRQ_DISABLED is set) by code running onanother CPU, then in this case we should not unmask the interrupt line (which we masked by calling the PIC related ack() function, line 583). If the IRQ is not yet disabled, this function end() will simply unmask the interrupt line at PIC level and return. After this we go ahead and do serve the pending softirqs (is any marked). We will see in next section what are siftirqs. I will soon post the details of softirqs, tasklets and bottom halfs, so keep looking for that on my blog.

Tags: interrupt, cpu, irq, line, gate

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